5000 Subscribers! Answering your frequently-asked questions!

Free FPGA training and resources!

Zynq Part 3: Combining my own HDL with the Vivado block diagram!

ILA in a Zynq: View signals in hardware!

Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM

Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

Is chatGPT going to take my job? How well can chatGPT write Verilog?

AXI Part 3: AXI-Lite testbench (briefly)

AXI Introduction Part 2: AXI-Lite state machine example explained!

AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

Reading from and writing to file: My PDM testbench from start to finish.

When and how to use the Multiplier IP core

FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!

Handling Ethernet FIFO overflows in SystemVerilog! How to keep packets intact above line rate!

Receiving packets over Ethernet using Python

How to use the clocking wizard IP: creating a 50Mhz clock from 100Mhz

A quick and easy Ethernet Frame state machine, explained from start to finish!

Digilent Nexys A7-100T Review!

My Linux + Vivado development environment!

Bloopers

Flashing a LED with Vivado and a Nexys A7 FPGA board: Step by step walkthrough!

Setting up a Nexys board in Linux!

Polynomial example part 2! Final window code with pipelining!

Tips for working on a engineering design team as an intern or new graduate!

Fixing failed timing, a practical example in verilog!

FPGA unboxing and chat: Why I started this channel and future plans!

Fixed point basics in Verilog for Beginners! Continuation of polynomial example.

How do I write to file? Testbench basics for beginners in Verilog!

Creating input and output delay constraints

Algorithm preparation for the FPGA: A polynomial window example