In this video, I have demonstrated the steps to follow to generate the symbol of Half Adder, whose simulation video I have uploaded before (link provided below).

The components generated by user are basically of the schematics that have been made before. So, these components can be used again and again, thereby reducing the work-load of making tideous circuits.

This technique is highly useful while making large circuits using CMOS, which will be shown in future videos.

Link for Half-adder simulation in LTspice:    • Half Adder simulation in LTSpice